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256-Position SPI/I2C Selectable Digital Potentiometer AD5161
FEATURES
256-position End-to-end resistance 5 k, 10 k, 50 k, 100 k Compact MSOP-10 (3 mm x 4.9 mm) package Pin selectable SPI/I2C compatible interface Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/C Low power, IDD = 8 A Wide operating temperature -40C to +125C SDO output allows multiple device daisy-chaining Evaluation board available
FUNCTIONAL BLOCK DIAGRAM
VDD SDI/SDA CLK/SCL DIS CS/AD0 SPI OR I2C INTERFACE W SDO/NC A
WIPER REGISTER
B
GND
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment
PIN CONFIGURATION
A1 B2 CS/ADO 3 SDI/SDA 5 10 W
AD5161
TOP VIEW SDO/NC 4 (Not to Scale) 7 GND 6 CLK/SCL
9 VDD 8 DIS
GENERAL OVERVIEW
The AD5161 provides a compact 3 mm x 4.9 mm packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. The wiper settings are controllable through a pin selectable SPI or I2C compatible digital interface, which can also be used to read back the wiper register content. When the SPI mode is used, the device can be daisy-chained (SDO to SDI), allowing several parts to share the same control lines. In the I2C mode, address pin AD0 can be used to place up to two devices on the same bus. In this same mode, command bits are available to reset the wiper position to midscale or to shut down the device into a state of zero power consumption. Operating from a 2.7 V to 5.5 V power supply and consuming less than 5 A allows for usage in portable battery-operated applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
Figure 2.
Note: The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5161 TABLE OF CONTENTS
Electrical Characteristics--5 k Version ...................................... 3 Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4 Timing Characteristics--5 k, 10 k, 50 k, 100 k Versions 5 Absolute Maximum Ratings1 .......................................................... 6 Typical Performance Characteristics ............................................. 7 Test Circuits..................................................................................... 11 SPI Interface .................................................................................... 12 I2C Interface..................................................................................... 13 Operation......................................................................................... 14 Programming the Variable Resistor ......................................... 14 Programming the Potentiometer Divider ............................... 15 Pin Selectable Digital Interface................................................. 15 Level Shifting for Bidirectional Interface ................................ 17 ESD Protection ........................................................................... 17 Terminal Voltage Operating Range.......................................... 17 Power-Up Sequence ................................................................... 17 Layout and Power Supply Bypassing ....................................... 17 Pin Configuration and Function Descriptions........................... 18 Pin Configuration ...................................................................... 18 Pin Function Descriptions ........................................................ 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19 ESD Caution................................................................................ 19
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5161 ELECTRICAL CHARACTERISTICS--5 k VERSION
(VDD = 5 V 10%, or 3 V 10%; VA = +VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted.) Table 1.
Parameter Symbol Conditions DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect Nominal Resistor Tolerance3 RAB TA = 25C Resistance Temperature Coefficient RAB/T VAB = VDD, Wiper = no connect Wiper Resistance RW DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N Differential Nonlinearity4 DNL Integral Nonlinearity4 INL Voltage Divider Temperature Coefficient VW/T Code = 0x80 Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA,B,W Capacitance6 A, B CA,B f = 1 MHz, measured to GND, Code = 0x80 Capacitance6 W CW f = 1 MHz, measured to GND, Code = 0x80 Shutdown Supply Current7 IDD_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH Input Logic Low VIL Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V 6 Input Capacitance CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = +5 V 10%, Code = Midscale DYNAMIC CHARACTERISTICS6, 9 Bandwidth -3dB BW_5K RAB = 5 k, Code = 0x80 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz VW Settling Time tS VA= 5 V, VB = 0 V, 1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 2.5 k, RS = 0 Min -1.5 -4 -30 Typ1 0.1 0.75 45 50 Max +1.5 +4 +30 120 8 +1.5 +1.5 0 +6 VDD 45 60 0.01 1 2.4 0.8 2.1 0.6 1 5 2.7 3 0.02 5.5 8 0.2 0.05 1 Unit LSB LSB % ppm/C Bits LSB LSB ppm/C LSB LSB V pF pF A nA V V V V A pF V A mW %/%
-1.5 -1.5 -6 0 GND
0.1 0.6 15 -2.5 +2
1.2 0.05 1 6
MHz % s nV/Hz
Rev. 0 | Page 3 of 20
AD5161 ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS
(VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted.) Table 2.
Parameter DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Symbol R-DNL R-INL RAB RAB/T Conditions Min -1 -2 -30 Typ1 0.1 0.25 45 50 120 8 +1 +1 0 3 VDD 45 60 0.01 1 2.4 0.8 2.1 0.6 1 5 2.7 3 5.5 8 0.2 0.05 1 Max +1 +2 +30 Unit LSB LSB % ppm/C Bits LSB LSB ppm/C LSB LSB V pF pF A nA V V V V A pF V A mW %/%
RWB, VA = no connect RWB, VA = no connect TA = 25C VAB = VDD, Wiper = no connect Wiper Resistance RW VDD = 5 V DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N Differential Nonlinearity4 DNL Integral Nonlinearity4 INL Voltage Divider Temperature Coefficient VW/T Code = 0x80 Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA,B,W Capacitance6 A, B CA,B f = 1 MHz, measured to GND, Code = 0x80 Capacitance6 W CW f = 1 MHz, measured to GND, Code = 0x80 Shutdown Supply Current7 IDD_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH Input Logic Low VIL Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance6 CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = +5 V 10%, Code = Midscale DYNAMIC CHARACTERISTICS6, 9 Bandwidth -3dB BW RAB = 10 k/50 k/100 k, Code = 0x80 Total Harmonic Distortion THDW VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VW Settling Time (10 k/50 k/100 k) tS VA = 5 V, VB = 0 V, 1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 5 k, RS = 0
-1 -1 -3 0 GND
0.1 0.3 15 -1 1
0.02
600/100/40 0.05 2 9
kHz % s nV/Hz
Rev. 0 | Page 4 of 20
AD5161 TIMING CHARACTERISTICS--5 k, 10 k, 50 k, 100 k VERSIONS
(VDD = +5V 10%, or +3V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted.) Table 3.
Parameter Symbol Conditions SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts) Clock Frequency fCLK Input Clock Pulsewidth tCH, tCL Clock level high or low Data Setup Time tDS Data Hold Time tDH tCSS CS Setup Time tCSW CS High Pulsewidth tCSH0 CLK Fall to CS Fall Hold Time tCSH1 CLK Fall to CS Rise Hold Time tCS1 CS Rise to Clock Rise Setup I2C INTERFACE TIMING CHARACTERISTICS6, 11 (Specifications Apply to All Parts) SCL Clock Frequency fSCL tBUF Bus Free Time between STOP and START t1 tHD;STA Hold Time (Repeated START) t2 After this period, the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time for Repeated START Condition t5 tHD;DAT Data Hold Time t6 tSU;DAT Data Setup Time t7 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU;STO Setup Time for STOP Condition t10 Min Typ1 Max 25 20 5 5 15 40 0 0 10 400 1.3 0.6 1.3 0.6 0.6 100 300 300 0.6 Unit MHz ns ns ns ns ns ns ns ns kHz s s s s s s ns ns ns s
50 0.9
NOTES 1 Typical specifications represent average readings at +25C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 8 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use VDD = 5 V. 10 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 11 See timing diagrams for locations of measured values.
Rev. 0 | Page 5 of 20
AD5161 ABSOLUTE MAXIMUM RATINGS1
(TA = +25C, unless otherwise noted.) Table 4
Parameter VDD to GND VA, VB, VW to GND IMAX1 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance2 JA: MSOP-10 Value -0.3 V to +7 V VDD 20 mA 0 V to +7 V -40C to +125C 150C -65C to +150C 300C 200C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTES 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA.
Rev. 0 | Page 6 of 20
AD5161 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8
1.0
5V 3V
POTENTIOMETER MODE DNL (LSB)
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
RHEOSTAT MODE INL (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
-40C +25C +85C +125C
0
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 3. R-INL vs. Code vs. Supply Voltages
1.0 0.8 5V 3V
1.0 0.8
POTENTIOMETER MODE INL (LSB)
Figure 6. DNL vs. Code, VDD = 5 V
RHEOSTAT MODE DNL (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192
5V 3V
224
256
224
256
CODE (Decimal)
CODE (Decimal)
Figure 4. R-DNL vs. Code vs. Supply Voltages
1.0 0.8
POTENTIOMETER MODE INL (LSB)
Figure 7. INL vs. Code vs. Supply Voltages
1.0
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192
POTENTIOMETER MODE DNL(LSB)
_40C +25C +85C +125C
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
5V 3V
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 5. INL vs. Code, VDD = 5 V
Figure 8. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page 7 of 20
AD5161
1.0 0.8
-40 C +25C +85C +125C
2.5
RHEOSTAT MODE INL (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
ZSE, ZERO-SCALE ERROR (A)
0.6
2.0 VDD = 5.5V
1.5
1.0
VDD = 2.7V
0.5
0 -40
0
40
80
120
TEMPERATURE (C)
Figure 9. R-INL vs. Code, VDD = 5 V
1.0 0.8
10
Figure 12. Zero-Scale Error vs. Temperature
RHEOSTAT MODE DNL (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192
+25C +85C +125C
IDD SUPPLY CURRENT (A)
_40C
VDD = 5.5V 1
VDD = 2.7V
224
256
0.1 -40
0
40
80
120
CODE (Decimal)
TEMPERATURE (C)
Figure 10. R-DNL vs. Code, VDD = 5 V
2.5
70 60
Figure 13. Supply Current vs. Temperature
FSE, FULL-SCALE ERROR (LSB)
IA SHUTDOWN CURRENT (nA)
2.0
50 40 30 20 10 VDD = 5V
1.5 VDD = 2.7V 1.0 VDD = 5.5V 0.5
0 -40
0
40
80
120
0 -40
0
40
80
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. Full-Scale Error vs. Temperature
Figure 14. Shutdown Current vs. Temperature
Rev. 0 | Page 8 of 20
AD5161
200
REF LEVEL 0.000dB 0 -6
/DIV 6.000dB
0x80 0x40 0x20 0x10 0x08 0x04
MARKER 510 634.725Hz MAG (A/R) -9.049dB
RHEOSTAT MODE TEMPCO (ppm/C)
150
-12 -18
100
-24 -30
50
-36 -42
0x02 0x01
0
-48 -54
-50 0 32 64 96 128 160 192 224 256 CODE (Decimal)
-60 1k START 1 000.000Hz 10k 100k 1M STOP 1 000 000.000Hz
Figure 15. Rheostat Mode Tempco RWB/T vs. Code
160
POTENTIOMETER MODE TEMPCO (ppm/C)
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 k
REF LEVEL 0.000dB 0 -6 -12 -18 -24 -30 -36 -42 -48 /DIV 6.000dB
0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01
MARKER 100 885.289Hz MAG (A/R) -9.014dB
140 120 100 80 60 40 20 0
-54
-20 0 32 64 96 128 160 192 224 256 CODE (Decimal)
-60 1k START 1 000.000Hz 10k 100k 1M STOP 1 000 000.000Hz
Figure 16. Potentiometer Mode Tempco VWB/T vs. Code
REF LEVEL 0.000dB 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 1k START 1 000.000Hz 10k 100k 1M STOP 1 000 000.000Hz /DIV 6.000dB
0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 k
REF LEVEL 0.000dB 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 1k START 1 000.000Hz 10k 100k 1M STOP 1 000 000.000Hz /DIV 6.000dB
0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01
MARKER 1 000 000.000Hz MAG (A/R) -8.918dB
MARKER 54 089.173Hz MAG (A/R) -9.052dB
Figure 17. Gain vs. Frequency vs. Code, RAB = 5 k
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 k
Rev. 0 | Page 9 of 20
AD5161
REF LEVEL -5.000dB -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 10k START 1 000.000Hz
R = 100k R = 10k R = 50k R = 5k
/DIV 0.500dB
5k - 1.026 MHz 10k - 511 MHz 50k - 101 MHz 100k - 54 MHz
1
VW
CLK 2 Ch 1 200mV BW Ch 2 5.00 V BW M 100ns A CH2 3.00 V
Figure 24. Digital Feedthrough
100k 1M 10M STOP 1 000 000.000Hz
Figure 21. -3 dB Bandwidth @ Code = 0x80
60 CODE = 0x80, VA= VDD, VB = 0V
VA = 5V VB = 0V
40
PSRR (dB)
1
VW
PSRR @ VDD = 3V DC 10% p-p AC
CS 2 Ch 1 100mV BW Ch 2 5.00 V BW M 200ns A CH1 152mV
20
PSRR @ VDD = 5V DC 10% p-p AC 0 100 1k 10k FREQUENCY (Hz) 100k 1M
Figure 25. Midscale Glitch, Code 0x80-0x7F
Figure 22. PSRR vs. Frequency
900 800 700 600 500 400 300 200 100 0 10k 100k 1M FREQUENCY (Hz) 10M CODE = 0x55 VDD = 5V
VA = 5V VB = 0V
1
VW
IDD (A)
CS
CODE = 0xFF
2 Ch 1 5.00V BW Ch 2 5.00 V BW M 200ns A CH1 3.00 V
Figure 26. Large Signal Settling Time, Code 0xFF-0x00
Figure 23. IDD vs. Frequency
Rev. 0 | Page 10 of 20
AD5161 TEST CIRCUITS
Figure 27 to Figure 35 illustrate the test circuits that define the test conditions used in the product specification tables.
DUT A V+ B W VMS
OFFSET GND A 5V OP279 VIN W DUT B VOUT
V+ = VDD 1LSB = V+/2N
OFFSET BIAS
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 32. Test Circuit for Noninverting Gain
NO CONNECT DUT A B VMS W OFFSET GND 2.5V IW
A VIN W DUT B
+15V
AD8610 -15V
VOUT
Figure 28. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure 33. Test Circuit for Gain vs. Frequency
DUT A VMS2 B VMS1 RW = [VMS1 - VMS2]/I W W VW I W = VDD /R NOMINAL
DUT W B ISW
RSW =
0.1V ISW
CODE = 0x00 0.1V
VSS TO VDD
Figure 29. Test Circuit for Wiper Resistance Figure 34. Test Circuit for Incremental ON Resistance
VA V+ = VDD 10% VDD V+ B PSRR (dB) = 20 LOG A W PSS (%/%) = VMS V MS% V DD%
(V MS ) DD
V
NC VDD VSS A B ICM VCM NC = NO CONNECT
DUT GND
W
NC
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
Figure 35. Test Circuit for Common-Mode Leakage current
A VIN OFFSET GND
DUT
B 5V W OP279 VOUT
OFFSET BIAS
Figure 31. Test Circuit for Inverting Gain
Rev. 0 | Page 11 of 20
AD5161 SPI INTERFACE
Table 5. AD5161 Serial Data-Word Format
B7 D7 MSB 27 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0 LSB 20
1
SDI
0 1
D7
D6
D5
D4
D3
D2
D1
D0
CLK CS VOUT
0 1 0 1 0
RDAC REGISTER LOAD
Figure 36. AD5161 SPI Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
1 SDI (DATA IN)
Dx
0 1
Dx tCH tDS tCH tCS1
CLK 0
tCSHO tCSS
tCL
tCSH1
1 CS 0
tCSW tS
VDD
VOUT 0 1LSB
Figure 37. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
Rev. 0 | Page 12 of 20
AD5161 I2C INTERFACE
Table 6. Write Mode
S 0 1 0 1 1 0 AD0 W A X RS SD X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 Data Byte A P Slave Address Byte Instruction Byte
Table 7. Read Mode
S 0 1 0 1 1 0 Slave Address Byte AD0 R A D7 D6 D5 D4 D3 Data Byte D2 D1 D0 A P
S = Start Condition P = Stop Condition A = Acknowledge X = Don't Care W = Write
R = Read RS = Reset wiper to Midscale 80H SD = Shutdown connects wiper to B terminal and open circuits A terminal. It does not change contents of wiper register. D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits
t8
SCL
t9
t2
t6 t2 t3 t8 t9 t4 t7 t5 t10
SDA
t1 P S S P
Figure 38. I2C Interface Detailed Timing Diagram
1 SCL SDA 0 1 0 1 1 0 AD0 R/W X RS SD X X X X X D7 D6 D5 D4 D3 D2 D1 D0 9 1 9 1 9
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
ACK BY AD5161
FRAME 2 INSTRUCTION BYTE
ACK BY AD5161
FRAME 3 DATA BYTE
ACK BY AD5161 STOP BY MASTER
Figure 39. Writing to the RDAC Register
1 SCL 0 1 0 1 1 0 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 9 1 9
SDA
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
ACK BY AD5161
FRAME 2 RDAC REGISTER
NO ACK BY MASTER STOP BY MASTER
Figure 40. Reading Data from a Previously Selected RDAC Register in Write Mode
Rev. 0 | Page 13 of 20
AD5161 OPERATION
The AD5161 is a 256-position digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. The general equation determining the digitally programmed output resistance between W and B is
RWB (D ) =
D
256
x R AB + R W
(1)
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
The nominal resistance of the RDAC between terminals A and B is available in 5 k, 10 k, 50 k, and 100 k. The final two or three digits of the part number determine the nominal resistance value, e.g., 10 k = 10; 50 k = 50. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a 10 k part is used, the wiper's first connection starts at the B terminal for data 0x00. Since there is a 60 wiper contact resistance, such connection yields a minimum of 60 resistance between terminals W and B. The second connection is the first tap point, which corresponds to 99 (RWB = RAB/256 + RW = 39 + 60 ) for data 0x01. The third connection is the next tap point, representing 177 (2 x 39 + 60 ) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 9961 (RAB - 1 LSB + RW). Figure 41 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance.
A
SD BIT
where D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register, RAB is the end-to-end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 10 k and the A terminal is open circuited, the following output resistance RWB will be set for the indicated RDAC latch codes. Table 8. Codes and Corresponding RWB Resistance
D (Dec.) 255 128 1 0 RWB () 9,961 5,060 99 60 Output State Full Scale (RAB - 1 LSB + RW) Midscale 1 LSB Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of 60 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is
RS
D7 D6 D5 D4 D3 D2 D1 D0
RS RS W
RWA (D ) =
256 - D x R AB + RW 256
(2)
For RAB = 10 k and the B terminal open circuited, the following output resistance RWA will be set for the indicated RDAC latch codes. Table 9. Codes and Corresponding RWA Resistance
D (Dec.) 255 128 1 0 RWA () 99 5,060 9,961 10,060 Output State Full Scale Midscale 1 LSB Zero Scale
RDAC LATCH RS AND DECODER
B
Figure 41. AD5161 Equivalent RDAC Circuit
Typical device to device matching is process lot dependent and may vary by up to 30%. Since the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 45 ppm/C temperature coefficient.
Rev. 0 | Page 14 of 20
AD5161
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A-to-B. Unlike the polarity of VDD to GND, which must be positive, voltage across A-B, W-A, and W-B can be at either polarity. If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is
internal RDAC register when the CS line returns to logic high. Extra MSB bits are ignored. Daisy-Chain Operation The serial data output (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor in order to transfer data to the next package's SDI pin. This allows for daisy-chaining several RDACs from a single processor serial data line. The pull-up resistor termination voltage can be larger than the VDD supply voltage. It is recommended to increase the clock period when using a pull-up resistor to the SDI pin of the following device because capacitive loading at the daisy-chain node SDO-SDI between devices may induce time delay to subsequent devices. Users should be aware of this potential problem to achieve data transfer successfully (see Figure 42). If two AD5161s are daisy-chained, a total of at least 16 bits of data is required. The first eight bits, complying with the format shown in Table 5, go to U2 and the second eight bits with the same format go to U1. CS should be kept low until all 16 bits are clocked into their respective serial registers. After this, CS is pulled high to complete the operation and load the RDAC latch. If the data word during the CS low period is greater than 16 bits, any additional MSBs will be discarded.
VDD
VW (D ) =
D
256
VA +
256 - D VB 256
(3)
For a more accurate calculation, which includes the effect of wiper resistance, VW, can be found as
VW (D ) =
RWB (D )
256
VA +
RWA (D )
256
VB
(4)
Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB and not the absolute values. Therefore, the temperature drift reduces to 15 ppm/C.
C
MOSI CLK SC
AD5161
U1 SDI CS SDO CLK
RP
AD5161
U2 SDI CS SDO CLK
2.2k
PIN SELECTABLE DIGITAL INTERFACE
The AD5161 provides the flexibility of a selectable interface. When the digital interface select (DIS) pin is tied low, the SPI mode is engaged. When the DIS pin is tied high, the I2C mode is engaged.
Figure 42. Daisy-Chain Configuration
SPI Compatible 3-Wire Serial Bus (DIS = 0)
The AD5161 contains a 3-wire SPI compatible digital interface (SDI, CS, and CLK). The 8-bit serial word must be loaded MSB first. The format of the word is shown in Table 5. The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. When CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 36). The data setup and data hold times in the specification table determine the valid timing requirements. The AD5161 uses an 8-bit serial input data register word that is transferred to the
I2C Compatible 2-Wire Serial Bus (DIS = 1)
The AD5161 can also be controlled via an I2C compatible serial bus with DIS tied high. The RDACs are connected to this bus as slave devices. The first byte of the AD5161 is a slave address byte (see Table 6 and Table 7). It has a 7-bit slave address and a R/W bit. The six MSBs of the slave address are 010110, and the following bit is determined by the state of the AD0 pin of the device. AD0 allows the user to place up to two of the I2C compatible devices on one bus. The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 39). The following byte is the slave address byte, which consists of
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AD5161
the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device. 2. A write operation contains an extra instruction byte that a read operation does not contain. Such an instruction byte in write mode follows the slave address byte. The first bit (MSB) of the instruction byte is a don't care. The second MSB, RS, is the midscale reset. A logic high on this bit moves the wiper to the center tap where RWA = RWB. This feature effectively writes over the contents of the register, and thus, when taken out of reset mode, the RDAC will remain at midscale. The third MSB, SD, is a shutdown bit. A logic high causes an open circuit at terminal A while shorting the wiper to terminal B. This operation yields almost 0 in rheostat mode or 0 V in potentiometer mode. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting will be applied to the RDAC. Also, during shutdown, new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting will be applied to the RDAC. The remainder of the bits in the instruction byte are don't cares (see Table 6). 3. After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Table 6). In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 40). 5. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 39). In read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse which goes high to establish a STOP condition (see Figure 40).
A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the write cycle, each data byte will update the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output will update after these two bytes. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. If different instructions are needed, the write mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed. Readback RDAC Value The AD5161 allows the user to read back the RDAC values in the read mode. Refer to Table 6 and Table 7 for the programming format. Multiple Devices on One Bus Figure 43 shows two AD5161 devices on the same serial bus. Each has a different slave address since the states of their AD0 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C compatible interface.
+5V
RP
RP
SDA MASTER SCL +5V SDA SCL AD0 SDA SCL AD0
4.
AD5161
AD5161
Figure 43. Multiple AD5161 Devices on One I2C Bus
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AD5161
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 44 shows one of the implementations. M1 and M2 can be any N-channel signal FETs, or if VDD falls below 2.5 V, low threshold FETs such as the FDV301N.
VDD1 = 3.3V RP RP G SDA1 SCL1 3.3V S M1 D G S M2 D 5V SDA2 SCL2 RP RP VDD2 = 5V
TERMINAL VOLTAGE OPERATING RANGE
The AD5161 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or GND will be clamped by the internal forward biased diodes (see Figure 47).
VDD
A
W
B VSS
Figure 47. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 47), it is important to power VDD/GND before applying any voltage to terminals A, B, and W; otherwise, the diode will be forward biased such that VDD will be powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA/B/W. The relative order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND.
E2PROM
AD5161
Figure 44. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 45 and Figure 46. This applies to the digital input pins SDI/SDA, CLK/SCL, and CS/AD0.
340 LOGIC
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 48). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.
VDD C3 + C1 10F 0.1F VDD
Vss
Figure 45. ESD Protection of Digital Pins
A,B,W
VSS
Figure 46. ESD Protection of Resistor Terminals
AD5161
GND
Figure 48. Power Supply Bypassing
Rev. 0 | Page 17 of 20
AD5161 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
A1 B2 CS/ADO 3 SDI/SDA 5 10 W
PIN FUNCTION DESCRIPTIONS
Table 10.
Pin 1 2 3 Name A B CS/AD0 Description A Terminal. B Terminal. CS: Chip Select Input, Active Low. When CS returns high, data will be loaded into the DAC register. AD0: Programmable address bit 0 for multiple package decoding. SDO: Serial Data Output. Open-drain transistor requires pull-up resistor. NC: No Connect. SDI: Serial Data Input. SDA: Serial Data Input/Output. Serial Clock Input. Positive edge triggered. Digital Ground. Digital Interface Select (SPI/I2C Select). SPI when DIS = 0, I2C when DIS = 1. Positive Power Supply. W Terminal.
AD5161
TOP VIEW SDO/NC 4 (Not to Scale) 7 GND 6 CLK/SCL
9 VDD 8 DIS
Figure 49.
4
SDO/NC
5 6 7 8 9 10
SDI/SDA CLK/SCL GND DIS VDD W
Rev. 0 | Page 18 of 20
AD5161 OUTLINE DIMENSIONS
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 1.10 MAX
SEATING PLANE
0.23 0.20 0.17
8 0
0.80 0.40
COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 50. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5161BRM5 AD5161BRM5-RL7 AD5161BRM10 AD5161BRM10-RL7 AD5161BRM50 AD5161BRM50-RL7 AD5161BRM100 AD5161BRM100-RL7 AD5161EVAL
1
RAB () 5k 5k 10k 10k 50k 50k 100k 100k See Note 1
Temperature -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 Evaluation Board
Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10
Branding D0C D0C D0D D0D D0E D0E D0F D0F
The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options.
The AD5161 contains 2532 transistors. Die size: 30.7 mil x 76.8 mil = 2358 sq. mil.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD5161 NOTES
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03435-0-5/03(0)
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